<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">Rick,<div class=""><br class=""></div><div class="">Are you running a lower power Ar plasma before/while de-chucking? Have a look at this:</div><div class=""><br class=""></div><div class=""><a href="http://www.google.com/patents/US20110151669" class="">http://www.google.com/patents/US20110151669</a></div><div class=""><br class=""></div><div class="">To summarize, here’s a cut-and-paste from the patent:</div><div class=""><br class=""></div><div class=""><p num="p-0024" style="color: rgb(34, 34, 34); font-family: Arial, sans-serif; font-size: 13px; line-height: 21.33333396911621px;" class="">As part of the de-chuck process, an argon de-chuck is performed, wherein argon is introduced into chamber <b class="">42</b> and a radio frequency (RF) power, for example, about 400 watts, is applied to ionize argon and generate argon plasma. The RF energy may be applied for about 10 seconds. It is expected that by applying the argon plasma, the accumulated charges built up in wafer <b class="">100</b> are at least partially neutralized. The argon de-chuck is part of the de-chuck process because it also has the effect of releasing wafer <b class="">100</b>.</p><p num="p-0025" style="color: rgb(34, 34, 34); font-family: Arial, sans-serif; font-size: 13px; line-height: 21.33333396911621px;" class="">During or after the period when the argon plasma is in chamber <b class="">42</b>, a reverse de-chuck voltage is applied to ESC <b class="">16</b> to de-chuck (release) wafer <b class="">100</b>. In an embodiment, the reverse de-chuck voltage (referred to as a high reverse de-chuck voltage hereinafter) is between about −650V and about −975V. Experiments have found that, advantageously, by limiting the reverse de-chuck voltage in this range, the JTAG failure that may occur to wafer <b class="">100</b> in the via-etching is significantly reduced. This range of the reverse de-chuck voltage is likely to be less negative than the low reverse de-chuck voltages that are also used for de-chuck, which low reverse de-chuck voltages may be about −1300V, for example. The reverse de-chuck voltage may be applied, for example, about 2 seconds, although a longer or shorter time may also be used.</p><p num="p-0026" style="color: rgb(34, 34, 34); font-family: Arial, sans-serif; font-size: 13px; line-height: 21.33333396911621px;" class="">After the de-chuck process, lift pins <b class="">14</b> are raised to lift up wafer <b class="">100</b>. Lift pins <b class="">14</b> are grounded and contact the backside of wafer <b class="">100</b>. Accordingly, charges that are accumulated in the exposed conductive features may be discharged through the backside of wafer <b class="">100</b>. Advantageously, due to the use of the high reverse de-chuck voltage, which has a magnitude of about 50 percent to about 75 percent of the low reverse de-chuck voltage, the JTAG failure is significantly reduced. Experiments performed on wafers have demonstrated that if a low reverse de-chuck voltage of −1300V (which was used in conventional via-etching processes) is used, after the formation of opening <b class="">22</b> (<figref idrefs="DRAWINGS" class="">FIG. 3</figref>) and the subsequent photo resist ashing, the voltage potentials on the respective wafers range between about 6.5V and about −0.1V, with the difference being about 6.6V. As a comparison, when a high reverse de-chuck voltage of −975V (an embodiment of the present invention) is used, after the etching and ashing process of opening <b class="">22</b>, the voltage potentials on the respective wafers range between about −1.3V and about −3.9V, with the difference being only about 2.6V. The significant reduction in the differences of voltage potentials on a same wafer indicates better charge neutralization in the embodiments of the present invention than in conventional methods, which results in lower JTAG failure rates.</p></div><div class=""><br class=""></div><div class="">Best,</div><div class="">Noah</div><div class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Mar 4, 2015, at 10:49 AM, Bob Henderson <<a href="mailto:bob.henderson@etchedintimeinc.com" class="">bob.henderson@etchedintimeinc.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="WordSection1" style="page: WordSection1; font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span style="color: rgb(31, 73, 125);" class="">Rick:<o:p class=""></o:p></span></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span style="color: rgb(31, 73, 125);" class=""> </span></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span style="color: rgb(31, 73, 125);" class="">Holy lightning bolt you do seem to have a discharge problem. You didn’t say if the wafer has oxide on both sides but assuming it does I would suggest stripping the oxide on the chuck side to avoid the charging problem you seem to have. An electrostatic chuck works much better if you have a conductive material or in this case a semiconductor material than a dielectric. Assuming you also helium backside cooling with your E-chuck this should also allow you to etch the oxide that is patterned without the need to run multiple cycles. Depending on the RF power you might have to lower it a bit to avoid reticulation of the photo resist. I also don’t understand why you are using 8 microns of resist as 1-2 microns should suffice assuming the resist: oxide selectivity is around 3:1. If you care to share your process recipe I might be able to help out some more. Bob Henderson<o:p class=""></o:p></span></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span style="color: rgb(31, 73, 125);" class=""> </span></div><div class=""><div style="border-style: solid none none; border-top-color: rgb(181, 196, 223); border-top-width: 1pt; padding: 3pt 0in 0in;" class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><b class=""><span style="font-size: 10pt; font-family: Tahoma, sans-serif;" class="">From:</span></b><span style="font-size: 10pt; font-family: Tahoma, sans-serif;" class=""><span class="Apple-converted-space"> </span><a href="mailto:labnetwork-bounces@mtl.mit.edu" class="">labnetwork-bounces@mtl.mit.edu</a> [<a href="mailto:labnetwork-bounces@mtl.mit.edu" class="">mailto:labnetwork-bounces@mtl.mit.edu</a>]<span class="Apple-converted-space"> </span><b class="">On Behalf Of<span class="Apple-converted-space"> </span></b>Morrison, Richard H., Jr.<br class=""><b class="">Sent:</b><span class="Apple-converted-space"> </span>Wednesday, March 04, 2015 5:08 AM<br class=""><b class="">To:</b><span class="Apple-converted-space"> </span><a href="mailto:labnetwork@mtl.mit.edu" class="">labnetwork@mtl.mit.edu</a><br class=""><b class="">Subject:</b><span class="Apple-converted-space"> </span>[labnetwork] Need help with RIE process<o:p class=""></o:p></span></div></div></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">Hi everyone,<o:p class=""></o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">I have a strange problem that I need some help with. We have an Ulvac NE-550 RIE system with an electrostatic chuck. The wafer is a double sided polish with 1um of SiO2. One side has an AZ4620 resist pattern 8um thick to etch the 1um of oxide. Because the process runs hot we break the etch into 9 different steps and move into the LL after every step. On the polished side that is down on the ESC check we have craters on the surface that look like a lightning strike or meteor strike, this is fairly deep several microns.<o:p class=""></o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">I have attached a photo of the damage. Have any of you seen anything like this? I need to fix the issue because the side that is down ends up being the frontside of the wafer and that is a killer defect. We think the oxide is charging and when the lift pins come up (at ground potential) we get a discharge.<o:p class=""></o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">Rick<o:p class=""></o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">Draper Laboratory<o:p class=""></o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">Principal Member of the Technical Staff<o:p class=""></o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">Group Leader Microfabrication Operations<o:p class=""></o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">555 Technology Square<o:p class=""></o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">Cambridge Ma, 02139-3563<o:p class=""></o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><a href="http://www.draper.com/" style="color: purple; text-decoration: underline;" class="">www.draper.com</a><o:p class=""></o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><a href="mailto:rmorrison@draper.com" style="color: purple; text-decoration: underline;" class="">rmorrison@draper.com</a><o:p class=""></o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">W 617-258-3420<o:p class=""></o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">C 508-930-3461<o:p class=""></o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div><div class="MsoNormal" align="center" style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; text-align: center;"><span style="font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><hr size="2" width="100%" align="center" class=""></span></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span style="font-size: 12pt; font-family: 'Times New Roman', serif;" class="">Notice: This email and any attachments may contain proprietary (Draper non-public) and/or export-controlled information of Draper Laboratory. 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