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<p class="MsoNormal">Dear colleagues,<o:p></o:p></p>
<p class="MsoNormal">Our group has been having a troublesome and seemingly random problem with pmma cracking during metalization steps, and I am hoping to get the community’s ideas on what might be causing the problem. Our typical process (used to make ohmic
contacts to III-V nanowire devices on Si/SiO2 substrates) is as follows:<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">PMMA 950K A4 spun at 4000 RPM (~200nm thickness)<o:p></o:p></p>
<p class="MsoNormal">Bake 175C 10 min<o:p></o:p></p>
<p class="MsoNormal">Expose 1100-1300 uC/cm^2 at 100kV<o:p></o:p></p>
<p class="MsoNormal">Develop 60s MIBK:IPA I:3, rinse in IPA 30s<o:p></o:p></p>
<p class="MsoNormal">60s O2 ashing (sample sits in Faraday cage, pmma etch rate ~1-3 nm/min)<o:p></o:p></p>
<p class="MsoNormal">Ammonium polysulfide passivation of III-V surface (sample sits in heavily diluted, super-saturated polysulfide solution at 60C for 30 min)<o:p></o:p></p>
<p class="MsoNormal">Quick load into evaporator followed by short in-situ He ion milling to remove residual sulfur layer<o:p></o:p></p>
<p class="MsoNormal">Evaporation of 10/120nm Cr/Au at 0.5/1.5 A/s. Vacuum level typically high 10^-8 Torr throughout deposition<o:p></o:p></p>
<p class="MsoNormal">Liftoff in acetone ~50C<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">The problem that we see is illustrated in the attached SEM image – thin filaments of metal extend from the contacts (typically starting at sharp corners) and short out devices. The fact that the cracks originate at sharp corners suggests
the issue is stress-related, but we have been unable to track down the cause of this excess stress. Many users (8-10) have seen this problem using different bottles of resist, different viscosities and molecular weights of pmma, different baking times and
temperatures (as short/cold as 5 min/150C and as hot/long as 190C/30min), different hotplates, 3 different e-beam lithography systems, a number of substrates/gate dielectrics (SiO2, SiNx, BN, InSb, sapphire), different metalization systems (two different e-beam
evaporators and one sputtering system – the helium etch is only done in one evaporator), different metalizations (Ti/Au, Cr/Au, NbTiN), and varying waiting times between spinning/exposure/developing/metalization (varying from 5 hours to 3 days for the whole
process). The process I described above had been stable for over a year until about a month ago when the cracking problem came up. Since then it has been sporadic, ruining a few (out of many) processing runs per week, but it has not been repeatable enough
to allow for really systematic testing. <o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Does anyone have any insight into what could increase stress in the resist? For instance, is temperature/humidity during spinning and baking particularly critical? One theory we are currently testing is that a recently instituted rule
of cleaning the spinners with a metal-ion-free photoresist developer following pmgi spinning could be causing the problem (e.g. this would help explain the random nature of the problem since it would depend on what the previous user did with the spinner).
Thanks,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">John<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><span lang="DE" style="font-size:10.0pt;mso-fareast-language:EN-GB">-----------------<br>
John Watson<br>
Postdoctoral Fellow - Kavli Institute of Nanoscience<br>
Delft University of Technology<br>
Lorentzweg 1, 2628 CJ Delft<br>
The Netherlands<br>
<br>
</span><span style="mso-fareast-language:EN-GB"><o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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