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<p class="MsoNormal">Hi Michael, et al –</p>
<p class="MsoNormal"><br>
</p>
<p class="MsoNormal">Good points, all.<span style="mso-spacerun:yes">
</span>For the last few years, we have been asking ourselves the
same questions, as we evolve from being predominately a
CMOS-compatible lab to one where most of our labmembers don’t
require this level of contamination control.<span
style="mso-spacerun:yes"> </span>It’s been a slower transition
than we’d like, because the process requires unraveling the why’s
of 60 years of best-known-practices, so we can figure out which
rules we can break with minimal risk.</p>
<p class="MsoNormal"><br>
</p>
<p class="MsoNormal">The main question is what level of technology
needs to be protected and to what degree.<span
style="mso-spacerun:yes"> </span>Our most demanding customers
are the detector researchers.<span style="mso-spacerun:yes"> </span>The
next most demanding are the Ge/SiGe device researchers.<span
style="mso-spacerun:yes"> </span>So, we try to make sure to
work with them to safeguard the high-risk process steps.<span
style="mso-spacerun:yes"> <br>
</span></p>
<p class="MsoNormal"><span style="mso-spacerun:yes"><br>
</span></p>
<p class="MsoNormal">The next step is to identify the process steps
where there is possible transfer of contaminants.<span
style="mso-spacerun:yes"> </span>Basically, RCA cleans done
before any high temperature step can rectify all sorts of assaults
to the system.<span style="mso-spacerun:yes"> </span>So at SNF,
we don’t dedicate litho equipment for reasons of contamination and
pretend that a CMOS substrate remains as CMOS clean when it leaves
litho.<span style="mso-spacerun:yes"> </span>There is basis for
this pretense - resist developers in the 80’s were NaOH-based, but
the post-etch resist cleans and pre-furnace RCA cleans were
sufficient for that generation of technology.<span
style="mso-spacerun:yes"> </span>However, it’s also important
to remember that temperatures don’t need to be very high for
mobile ions to start migrating – a high density plasma asher can
get hot enough, so it’s advisable to carefully review the process
runsheet.</p>
<p class="MsoNormal"><br>
</p>
<p class="MsoNormal">Depending on the stringency of your device
requirements, it’s possible to share CMOS and non-CMOS processes
on a single tool.<span style="mso-spacerun:yes"> </span>You
might be able to do a chamber clean or have dedicated cassettes,
handlers, of inserts.<span style="mso-spacerun:yes"> </span>You
might be able to lay down a barrier or getter layer in a
deposition system.<span style="mso-spacerun:yes"> </span>You
might be able to run a Cl-based clean cycle in an oxidation
furnace.</p>
<p class="MsoNormal"><br>
</p>
<p class="MsoNormal">Lastly, every time a device run fails, the very
first suspect is contamination.<span style="mso-spacerun:yes"> </span>More
often, it’s not, but rather because researchers often unknowingly
violate 60 years of process integration best-practices with
seemingly innocuous process changes (evaporating vs sputtering
metal, damaging gates; changing barrier metal, resulting in
spiking) or misprocessing (wrong implant dose).<span
style="mso-spacerun:yes"> </span>This is where careful review
of the process runsheet with an experienced integration person can
really save a lot of time and frustration. If you are building a
process from scratch, it's best to build up from modules.</p>
<p class="MsoNormal"><br>
</p>
<p class="MsoNormal">I am far from expert, but will gladly share our
experiences - and can refer you to the real experts.</p>
<p class="MsoNormal"><br>
</p>
<p class="MsoNormal">Best,</p>
<p class="MsoNormal"><br>
</p>
<p class="MsoNormal">Mary</p>
<p class="MsoNormal"><br>
</p>
<p class="MsoNormal"><span class="moz-txt-tag">-- <br>
</span>Mary X. Tang, Ph.D.
<br>
Managing Director<br>
Stanford Nanofabrication Facility
<br>
Paul G. Allen Building, Rm 141
<br>
420 Via Palou Mall
<br>
Stanford, CA 94305
<br>
(650)723-9980
<br>
<a class="moz-txt-link-abbreviated"
href="mailto:mtang@stanford.edu">mtang@stanford.edu</a>
<br>
<a class="moz-txt-link-freetext" href="https://snf.stanford.edu">https://snf.stanford.edu</a>
<br>
</p>
<p class="MsoNormal"><br>
</p>
<p class="MsoNormal"><br>
</p>
<p class="MsoNormal"><br>
</p>
<div class="moz-cite-prefix">On 3/20/2019 7:09 AM, Rehn, Larry A
wrote:<br>
</div>
<blockquote type="cite"
cite="mid:98970e3513f04e51806c9b4028476c83@tamu.edu">
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<div class="WordSection1">
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Hello
Michael,<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">I
general, I would say that you need to be most careful to
control any processes the involve elevated temperature, or
cleanups that occur before steps with high temperature. I
would suggest dedicated quartz containers for piranha
cleans. Besides suggestions from Matt below, I would
concentrate first on your oxidation and furnace operations.
It is best to have dedicated oxidation tubes that never see
any other materials except silicon and oxides, particularly
metal for annealing , sintering etc. In fact most would
have a dedicated field ox tube and a separate tube just for
the gate oxidation step, which is the most critical. If you
only have one furnace, then you will need to change out
quartz tubes (and push rods, wafer boats, profile
thermocouples, etc) for each operation. When you fabricate
the CMOS device it is also important to control any other
sources for Na+ contamination. Will you be using
polysilicon gates, or metal? If metal, than there are other
process tricks to make sure the gate integrity is
preserved.
<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">There
are also some ongoing things that are done to maintain
cleanliness of the system. Cleaning of tubes with dilute
HF, monitoring the gate/oxide device performance with CV
tests will ensure that you do not have too much mobile ion
concentration to affect the device.<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Good
luck!<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Larry
A Rehn<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Technical
Lab Manager<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">AggieFab
Nanofabrication Facility<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Texas
A&M University<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">979
845-3199<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><a
href="mailto:lrehn@tamu.edu" moz-do-not-send="true"><span
style="color:#0563C1">lrehn@tamu.edu</span></a><o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><img
id="Picture_x0020_2"
src="cid:part4.216F4BA7.C825256B@stanford.edu"
alt="cid:image001.jpg@01CEC37D.FAF8C9E0" class=""
width="300" height="73" border="0"><o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<div>
<div style="border:none;border-top:solid #E1E1E1
1.0pt;padding:3.0pt 0in 0in 0in">
<p class="MsoNormal"><b><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">
<a class="moz-txt-link-abbreviated" href="mailto:labnetwork-bounces@mtl.mit.edu">labnetwork-bounces@mtl.mit.edu</a>
[<a class="moz-txt-link-freetext" href="mailto:labnetwork-bounces@mtl.mit.edu">mailto:labnetwork-bounces@mtl.mit.edu</a>]
<b>On Behalf Of </b>Matthew Moneck<br>
<b>Sent:</b> Tuesday, March 19, 2019 11:59 AM<br>
<b>To:</b> Martin,Michael David
<a class="moz-txt-link-rfc2396E" href="mailto:michael.martin@louisville.edu"><michael.martin@louisville.edu></a>;
<a class="moz-txt-link-abbreviated" href="mailto:labnetwork@mtl.mit.edu">labnetwork@mtl.mit.edu</a><br>
<b>Subject:</b> Re: [labnetwork] CMOS Clean in a MEMS
Fab Facility<o:p></o:p></span></p>
</div>
</div>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597">Hi
Michael,<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597"><o:p> </o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597">Our
fab does not do a lot of traditional CMOS work, so I am by
no means an expert in this area. A lot of our work is
concentrated in MEMS (including back-end processing on CMOS
tapeout chips), magnetics, spintronics, photonics, 2D
materials, functional oxides, bio interfaces, other emerging
technologies. However, I can hopefully offer a few comments
from lessons learned or experiences we’ve had in the past,
especially when working on devices where trapped charge or
ion contamination were an issue.
<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597"><o:p> </o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597">Referencing
your original question numbers:<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597"><o:p> </o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597">1.
We typically use PTFE petri dishes for this application. We
routinely process 100mm wafers in low profile evaporating
dishes. While not cheap, a couple dishes won’t typically
set you back too much. <o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597"><o:p> </o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597">2.
We separate glassware for metal ion free (MIF) and metal ion
containing (MIC) containers (I’m assuming you are using MIF
developers for CMOS). Beakers are labeled MIF or MIC by
etching the letters into the glass exterior of the beaker.
If I recall correctly most of the beakers are
<span style="background:white">Type 1, Class A, 33 expansion
Borosilicate glass (note that I’m not endorsing this one
way or the other for CMOS).
<o:p></o:p></span></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597;background:white"> <o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597;background:white">2A.
We do not have a dedicated spinner for CMOS, but we do limit
which resists can go in which spinners (in the case where
non-standard resists are used).<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597;background:white"><o:p> </o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597;background:white">2B.
I would verify the type of glass used in the amber bottles.
Also, we buy droppers in clean, sterile packaging, as we
have seen that droppers packaged and stored incorrectly can
introduce contaminates. In extreme cases, we have had some
users request and move to glass pipettes.
<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597;background:white"><o:p> </o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597;background:white">2C.
The shared bath of NMP would be one of my biggest concerns
in this whole process. Manufacturers will list that NMP is
safe on a lot of metals, including copper. However, there
is a caveat. If the NMP bath collects or becomes
contaminated with moisture, it makes the bath corrosive. I
have seen first-hand how NMP can corrode, or even etch
through metals, such as copper. If people are using the
bath with such materials, it could have trace metals and
other contaminants.
<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597;background:white"><o:p> </o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597;background:white">We
do not do a lot in the way of furnace work, so I will
default to others in the network that are much more of an
expert in this area than me, but for what it’s worth, the
latter questions on quartz tube contaminants would be a
concern in my opinion. Even in simple annealing furnaces
and our RTA, we keep “clean” and “dirty” tubes/chambers that
we exchange depending on the materials being used. In
regards to potential vendors, we have purchased quartz
products from Technical Glass Products in the past (<a
href="https://urldefense.proofpoint.com/v2/url?u=https-3A__technicalglass.com_&d=DwMFAg&c=ODFT-G5SujMiGrKuoJJjVg&r=viXbs6wGaGZ-o2y0LFbqZrWN_jy4Cw47zl8d3Wrr2M4&m=xcsoSqLZ1td4AHsfpW_fG71YxxRin21Y89KQILp8A30&s=EaQ94Wv0hwJQ6Bky1QAe9J_xVZTqpH7I525wec8_bPg&e="
moz-do-not-send="true"><span style="color:#0000BF">https://technicalglass.com/</span></a>),
although, again, others who do a lot more work with furnaces
will likely have more input than me.
<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597;background:white"><o:p> </o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597;background:white">Hope
this helps in some capacity.
<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597;background:white"><o:p> </o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597;background:white">Best
Regards,<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597;background:white"><br>
Matt</span><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#2F5597"><o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<div>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">--
<br>
<b>Matthew T. Moneck, Ph.D.</b><br>
Executive Manager, Claire & John Bertucci
Nanotechnology Laboratory<br>
Electrical and Computer Engineering | Carnegie Mellon
University<br>
5000 Forbes Ave., Pittsburgh, PA 15213-3890<br>
T: 412.268.5430<br>
F: 412.268.3497<br>
<a
href="https://urldefense.proofpoint.com/v2/url?u=http-3A__www.ece.cmu.edu_&d=DwMFAg&c=ODFT-G5SujMiGrKuoJJjVg&r=viXbs6wGaGZ-o2y0LFbqZrWN_jy4Cw47zl8d3Wrr2M4&m=xcsoSqLZ1td4AHsfpW_fG71YxxRin21Y89KQILp8A30&s=yTWyjWfxzDFxrSZSFCC3jDg83rT8xIXzXQtGhcpAREQ&e="
moz-do-not-send="true">www.ece.cmu.edu</a><br>
nanofab.ece.cmu.edu<o:p></o:p></span></p>
</div>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<div>
<div style="border:none;border-top:solid #E1E1E1
1.0pt;padding:3.0pt 0in 0in 0in">
<p class="MsoNormal"><b><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">
<a href="mailto:labnetwork-bounces@mtl.mit.edu"
moz-do-not-send="true">labnetwork-bounces@mtl.mit.edu</a>
[<a href="mailto:labnetwork-bounces@mtl.mit.edu"
moz-do-not-send="true">mailto:labnetwork-bounces@mtl.mit.edu</a>]
<b>On Behalf Of </b>Martin,Michael David<br>
<b>Sent:</b> Monday, March 18, 2019 2:07 PM<br>
<b>To:</b> <a href="mailto:labnetwork@mtl.mit.edu"
moz-do-not-send="true">labnetwork@mtl.mit.edu</a><br>
<b>Subject:</b> [labnetwork] CMOS Clean in a MEMS Fab
Facility<o:p></o:p></span></p>
</div>
</div>
<p class="MsoNormal"><o:p> </o:p></p>
<div>
<p class="MsoNormal"><span
style="font-family:"Calibri",sans-serif;color:black">Hi,
<o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Calibri",sans-serif;color:black">
I'm trying to track down potential sources of
contamination for a CMOS process we are trying to run
through our predominantly MEMS fab here at U of
Louisville. Really the only pieces of equipment that are
dedicated for CMOS type processes is our RCA bench, an
older Technics sputterer, and our oxidation furnace (sort
of, see below). So I have a few questions for those of you
who have experience with this:
<o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Calibri",sans-serif;color:black">1)
For HF etch/dips is there a particular polymer type or
brand we should use for our containers that are known to
be free of trace metals? Can I avoid PTFE as this is super
expensive?
<o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Calibri",sans-serif;color:black">2)
When you do litho do you have separate labware for
developing? We currently use a Pyrex pan develop which I
know is a No-No due to Na and other ions. What sort of
container does your lab use (assuming pan develop)? <o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Calibri",sans-serif;color:black">
2 a) Do you have a dedicated spinner for CMOS?
<o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Calibri",sans-serif;color:black">
2 b) Is there any danger that we are picking up
contamination from the amber bottles we are temporarily
storing our resists in? What about the polypropylene
droppers we are dispensing resists with? <o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Calibri",sans-serif;color:black">
2 c) What about resist stripping after etching? We
typically use a big warm vat of NMP that is shared by all
users. We can also do a plasma etch but I worry about
carry over from other folks as none of our plasma etchers
are dedicated CMOS. <o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Calibri",sans-serif;color:black">3)
I presume quartz glassware works for my metal (usually
aluminum) etching? Do you do regular aqua regia cleans on
quartz-ware to scavenge other metals and potential
contaminants? <o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Calibri",sans-serif;color:black">4)
We gravitate to peek tipped metal tweezers. Are they
okay? Do you regularly run the tips through a RCA clean?
<o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Calibri",sans-serif;color:black">5)
Oxidation furnace: Before trying to transition to CMOS
like devices the tube was used with non-RCA cleaned wafers
and a pyrex bubbler. After moving to a quartz bubbler with
DI water we cleaned the 4" tube with HF. This is the one
I'm really concerned about because I'm guessing that ionic
contamination that might have been removed from the
surface will readily diffuse back at 1000C. So should we
just bite the bullet and buy a new tube? Any vendor
suggestions for a 4" Blue-M? <o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Calibri",sans-serif;color:black">6)
Any other suggestions other than buying a dedicated CMOS
tool set?
<o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Calibri",sans-serif;color:black"><o:p> </o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Calibri",sans-serif;color:black">I
did find a very nice document from Stanford that has a lot
of practical suggestions found here
<a
href="https://urldefense.proofpoint.com/v2/url?u=https-3A__web.stanford.edu_class_ee410_cleaning.pdf&d=DwMFAg&c=ODFT-G5SujMiGrKuoJJjVg&r=viXbs6wGaGZ-o2y0LFbqZrWN_jy4Cw47zl8d3Wrr2M4&m=xcsoSqLZ1td4AHsfpW_fG71YxxRin21Y89KQILp8A30&s=lekItA7Hi5mB01_AWgTSdp3AJDQnHLLdzAcqSCbAjWw&e="
id="LPlnk395163" moz-do-not-send="true">
https://web.stanford.edu/class/ee410/cleaning.pdf</a> )<o:p></o:p></span></p>
</div>
<div style="margin-top:12.0pt;margin-bottom:12.0pt;max-width:
800px;min-width: 424px"
id="LPBorder_GTaHR0cHM6Ly93ZWIuc3RhbmZvcmQuZWR1L2NsYXNzL2VlNDEwL2NsZWFuaW5nLnBkZg..">
<table class="MsoNormalTable" style="width:100.0%;border:solid
#C8C8C8 1.0pt" width="100%" cellpadding="0" border="1">
<tbody>
<tr>
<td style="width:100.0%;border:none;padding:9.0pt 27.0pt
9.0pt 9.0pt" width="100%" valign="top">
<div style="margin-right:6.0pt;margin-bottom:9.0pt"
id="LPTitle778519">
<p class="MsoNormal"><span
style="font-size:16.0pt;font-family:"Segoe
UI Light",sans-serif"><a
href="https://urldefense.proofpoint.com/v2/url?u=https-3A__web.stanford.edu_class_ee410_cleaning.pdf&d=DwMFAg&c=ODFT-G5SujMiGrKuoJJjVg&r=viXbs6wGaGZ-o2y0LFbqZrWN_jy4Cw47zl8d3Wrr2M4&m=xcsoSqLZ1td4AHsfpW_fG71YxxRin21Y89KQILp8A30&s=lekItA7Hi5mB01_AWgTSdp3AJDQnHLLdzAcqSCbAjWw&e="
target="_blank" moz-do-not-send="true"><span
style="text-decoration:none">Krishna Saraswa
- Stanford University</span></a><o:p></o:p></span></p>
</div>
<div
style="margin-right:6.0pt;margin-bottom:9.0pt;max-height:100px;overflow:hidden"
id="LPDescription778519">
<p class="MsoNormal"><span
style="font-size:10.5pt;font-family:"Segoe
UI",sans-serif;color:#666666">6 tanford
University araswat 11! Cleaning - Surface Issues
Contaminant • Organics – Skin oils – Resist –
Polymers • Metals<o:p></o:p></span></p>
</div>
<div id="LPMetadata778519">
<p class="MsoNormal"><span
style="font-size:10.5pt;font-family:"Segoe
UI",sans-serif;color:#A6A6A6">web.stanford.edu<o:p></o:p></span></p>
</div>
</td>
</tr>
</tbody>
</table>
</div>
<p class="MsoNormal"><o:p> </o:p></p>
<div>
<p class="MsoNormal">Thank you in advance, <o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"> Michael <o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"> <o:p></o:p></p>
</div>
</div>
<br>
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