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Thank you everyone for taking the time to respond! I thought I would summarize the key take-aways on trying to move aspects of our MEMS fab to CMOS. First, though Mary to your point: we are actually trying to do some Ge on Silicon devices and this is what is
driving the changes. Larry, we are using metal gates (Al-Si).<span style="mso-spacerun:yes">
</span>You mentioned “other tricks” for this case? Can you elaborate? <br>
</p>
<p style="margin: 0in 0in 8pt; line-height: 107%; font-size: 11pt; font-family: "Calibri", sans-serif">
Changes I'd like to implement: <br>
</p>
<ol style="margin-bottom: 0in">
<li>RCA Cleans before any “high” temperature process steps where “high” temperatures might be locally induced by aggressive plasma based processes.<span style="mso-spacerun:yes">
</span>Fortunately, we have a dedicated RCA bench.<span style="mso-spacerun:yes">
</span></li><li>Dedicated quartz or Teflon containers for lithography, Piranha cleans, and aluminum etch.<span style="mso-spacerun:yes">
</span>Separate containers for aluminum lithography vs. completely metal free wafers?
</li><li>We have had a dedicated furnace tube for some time but it was made “compatible” after years of general oxidation use by an aggressive HF etch.<span style="mso-spacerun:yes">
</span>I don’t think this is sufficient and will buy a new tube, rod, boat, etc…</li><li>We will begin monitoring contamination by regular CV tests </li><li>We will continue to use disposable polypropylene droppers for resist dispensing and amber bottles for CMOS resists</li><li>I will ask the management to set aside a spinner for CMOS compatible resists only with a particular emphasis on potential contamination from AZ 400k resists. We will stick to the Shipley S series.
</li><li>Dedicated CMOS container for either NMP, piranha or other resist removal solvents.
<span style="mso-spacerun:yes"> </span><br>
<br>
Thank you again!<span style="mso-spacerun:yes"> </span><br>
Regards, </li></ol>
<p style="margin: 0in 0in 8pt 0.5in; line-height: 107%; font-size: 11pt; font-family: "Calibri", sans-serif">
<span style="mso-spacerun:yes"> </span>Michael </p>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Mary Tang <mtang@stanford.edu><br>
<b>Sent:</b> Wednesday, March 20, 2019 5:17 PM<br>
<b>To:</b> Rehn, Larry A; Matthew Moneck; Martin,Michael David; labnetwork@mtl.mit.edu<br>
<b>Subject:</b> Re: [labnetwork] CMOS Clean in a MEMS Fab Facility</font>
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<p class="x_MsoNormal">Hi Michael, et al –</p>
<p class="x_MsoNormal"><br>
</p>
<p class="x_MsoNormal">Good points, all.<span style=""> </span>For the last few years, we have been asking ourselves the same questions, as we evolve from being predominately a CMOS-compatible lab to one where most of our labmembers don’t require this level
of contamination control.<span style=""> </span>It’s been a slower transition than we’d like, because the process requires unraveling the why’s of 60 years of best-known-practices, so we can figure out which rules we can break with minimal risk.</p>
<p class="x_MsoNormal"><br>
</p>
<p class="x_MsoNormal">The main question is what level of technology needs to be protected and to what degree.<span style="">
</span>Our most demanding customers are the detector researchers.<span style="">
</span>The next most demanding are the Ge/SiGe device researchers.<span style="">
</span>So, we try to make sure to work with them to safeguard the high-risk process steps.<span style="">
<br>
</span></p>
<p class="x_MsoNormal"><span style=""><br>
</span></p>
<p class="x_MsoNormal">The next step is to identify the process steps where there is possible transfer of contaminants.<span style="">
</span>Basically, RCA cleans done before any high temperature step can rectify all sorts of assaults to the system.<span style="">
</span>So at SNF, we don’t dedicate litho equipment for reasons of contamination and pretend that a CMOS substrate remains as CMOS clean when it leaves litho.<span style="">
</span>There is basis for this pretense - resist developers in the 80’s were NaOH-based, but the post-etch resist cleans and pre-furnace RCA cleans were sufficient for that generation of technology.<span style="">
</span>However, it’s also important to remember that temperatures don’t need to be very high for mobile ions to start migrating – a high density plasma asher can get hot enough, so it’s advisable to carefully review the process runsheet.</p>
<p class="x_MsoNormal"><br>
</p>
<p class="x_MsoNormal">Depending on the stringency of your device requirements, it’s possible to share CMOS and non-CMOS processes on a single tool.<span style="">
</span>You might be able to do a chamber clean or have dedicated cassettes, handlers, of inserts.<span style="">
</span>You might be able to lay down a barrier or getter layer in a deposition system.<span style="">
</span>You might be able to run a Cl-based clean cycle in an oxidation furnace.</p>
<p class="x_MsoNormal"><br>
</p>
<p class="x_MsoNormal">Lastly, every time a device run fails, the very first suspect is contamination.<span style="">
</span>More often, it’s not, but rather because researchers often unknowingly violate 60 years of process integration best-practices with seemingly innocuous process changes (evaporating vs sputtering metal, damaging gates; changing barrier metal, resulting
in spiking) or misprocessing (wrong implant dose).<span style=""> </span>This is where careful review of the process runsheet with an experienced integration person can really save a lot of time and frustration. If you are building a process from scratch,
it's best to build up from modules.</p>
<p class="x_MsoNormal"><br>
</p>
<p class="x_MsoNormal">I am far from expert, but will gladly share our experiences - and can refer you to the real experts.</p>
<p class="x_MsoNormal"><br>
</p>
<p class="x_MsoNormal">Best,</p>
<p class="x_MsoNormal"><br>
</p>
<p class="x_MsoNormal">Mary</p>
<p class="x_MsoNormal"><br>
</p>
<p class="x_MsoNormal"><span class="x_moz-txt-tag">-- <br>
</span>Mary X. Tang, Ph.D. <br>
Managing Director<br>
Stanford Nanofabrication Facility <br>
Paul G. Allen Building, Rm 141 <br>
420 Via Palou Mall <br>
Stanford, CA 94305 <br>
(650)723-9980 <br>
<a class="x_moz-txt-link-abbreviated" href="mailto:mtang@stanford.edu">mtang@stanford.edu</a>
<br>
<a class="x_moz-txt-link-freetext" href="https://urldefense.proofpoint.com/v2/url?u=https-3A__snf.stanford.edu&d=DwMD-g&c=OAG1LQNACBDguGvBeNj18Swhr9TMTjS-x4O_KuapPgY&r=Aa_3i0EVmeU66ldCX7R6J2GTszXqPwycgveGLP4hBZI&m=qYr5p6prpPkgoSO-asJHob1dRVPC91Tm-ikihz9dtEY&s=2SGWZh16QxTiF310BFptT026eVZ79XX9AGFk9-MCF4E&e=">https://snf.stanford.edu</a>
<br>
</p>
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<div class="x_moz-cite-prefix">On 3/20/2019 7:09 AM, Rehn, Larry A wrote:<br>
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<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#1F497D">Hello Michael,</span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#1F497D"> </span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#1F497D">I general, I would say that you need to be most careful to control any processes the involve elevated temperature, or cleanups that occur before steps with
high temperature. I would suggest dedicated quartz containers for piranha cleans. Besides suggestions from Matt below, I would concentrate first on your oxidation and furnace operations. It is best to have dedicated oxidation tubes that never see any other
materials except silicon and oxides, particularly metal for annealing , sintering etc. In fact most would have a dedicated field ox tube and a separate tube just for the gate oxidation step, which is the most critical. If you only have one furnace, then
you will need to change out quartz tubes (and push rods, wafer boats, profile thermocouples, etc) for each operation. When you fabricate the CMOS device it is also important to control any other sources for Na+ contamination. Will you be using polysilicon
gates, or metal? If metal, than there are other process tricks to make sure the gate integrity is preserved.
</span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#1F497D"> </span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#1F497D">There are also some ongoing things that are done to maintain cleanliness of the system. Cleaning of tubes with dilute HF, monitoring the gate/oxide device
performance with CV tests will ensure that you do not have too much mobile ion concentration to affect the device.</span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#1F497D"> </span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#1F497D">Good luck!</span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#1F497D">Larry A Rehn</span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#1F497D">Technical Lab Manager</span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#1F497D">AggieFab Nanofabrication Facility</span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#1F497D">Texas A&M University</span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#1F497D">979 845-3199</span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#1F497D"><a href="mailto:lrehn@tamu.edu"><span style="color:#0563C1">lrehn@tamu.edu</span></a></span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#1F497D"><img id="x_Picture_x0020_2" alt="cid:image001.jpg@01CEC37D.FAF8C9E0" class="" width="300" height="73" border="0" data-outlook-trace="F:1|T:1" src="cid:part4.216F4BA7.C825256B@stanford.edu"></span></p>
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<p class="x_MsoNormal"><b><span style="font-size:11.0pt; font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt; font-family:"Calibri",sans-serif">
<a class="x_moz-txt-link-abbreviated" href="mailto:labnetwork-bounces@mtl.mit.edu">
labnetwork-bounces@mtl.mit.edu</a> [<a class="x_moz-txt-link-freetext" href="mailto:labnetwork-bounces@mtl.mit.edu">mailto:labnetwork-bounces@mtl.mit.edu</a>]
<b>On Behalf Of </b>Matthew Moneck<br>
<b>Sent:</b> Tuesday, March 19, 2019 11:59 AM<br>
<b>To:</b> Martin,Michael David <a class="x_moz-txt-link-rfc2396E" href="mailto:michael.martin@louisville.edu">
<michael.martin@louisville.edu></a>; <a class="x_moz-txt-link-abbreviated" href="mailto:labnetwork@mtl.mit.edu">
labnetwork@mtl.mit.edu</a><br>
<b>Subject:</b> Re: [labnetwork] CMOS Clean in a MEMS Fab Facility</span></p>
</div>
</div>
<p class="x_MsoNormal"> </p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597">Hi Michael,</span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597"> </span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597">Our fab does not do a lot of traditional CMOS work, so I am by no means an expert in this area. A lot of our work is concentrated in MEMS (including back-end
processing on CMOS tapeout chips), magnetics, spintronics, photonics, 2D materials, functional oxides, bio interfaces, other emerging technologies. However, I can hopefully offer a few comments from lessons learned or experiences we’ve had in the past, especially
when working on devices where trapped charge or ion contamination were an issue.
</span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597"> </span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597">Referencing your original question numbers:</span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597"> </span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597">1. We typically use PTFE petri dishes for this application. We routinely process 100mm wafers in low profile evaporating dishes. While not cheap, a couple
dishes won’t typically set you back too much. </span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597"> </span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597">2. We separate glassware for metal ion free (MIF) and metal ion containing (MIC) containers (I’m assuming you are using MIF developers for CMOS). Beakers
are labeled MIF or MIC by etching the letters into the glass exterior of the beaker. If I recall correctly most of the beakers are
<span style="background:white">Type 1, Class A, 33 expansion Borosilicate glass (note that I’m not endorsing this one way or the other for CMOS).
</span></span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597; background:white"> </span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597; background:white">2A. We do not have a dedicated spinner for CMOS, but we do limit which resists can go in which spinners (in the case where non-standard
resists are used).</span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597; background:white"> </span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597; background:white">2B. I would verify the type of glass used in the amber bottles. Also, we buy droppers in clean, sterile packaging, as we have seen that
droppers packaged and stored incorrectly can introduce contaminates. In extreme cases, we have had some users request and move to glass pipettes.
</span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597; background:white"> </span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597; background:white">2C. The shared bath of NMP would be one of my biggest concerns in this whole process. Manufacturers will list that NMP is safe on a lot
of metals, including copper. However, there is a caveat. If the NMP bath collects or becomes contaminated with moisture, it makes the bath corrosive. I have seen first-hand how NMP can corrode, or even etch through metals, such as copper. If people are
using the bath with such materials, it could have trace metals and other contaminants.
</span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597; background:white"> </span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597; background:white">We do not do a lot in the way of furnace work, so I will default to others in the network that are much more of an expert in this area than
me, but for what it’s worth, the latter questions on quartz tube contaminants would be a concern in my opinion. Even in simple annealing furnaces and our RTA, we keep “clean” and “dirty” tubes/chambers that we exchange depending on the materials being used.
In regards to potential vendors, we have purchased quartz products from Technical Glass Products in the past (<a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__technicalglass.com_&d=DwMFAg&c=ODFT-G5SujMiGrKuoJJjVg&r=viXbs6wGaGZ-o2y0LFbqZrWN_jy4Cw47zl8d3Wrr2M4&m=xcsoSqLZ1td4AHsfpW_fG71YxxRin21Y89KQILp8A30&s=EaQ94Wv0hwJQ6Bky1QAe9J_xVZTqpH7I525wec8_bPg&e="><span style="color:#0000BF">https://technicalglass.com/</span></a>),
although, again, others who do a lot more work with furnaces will likely have more input than me.
</span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597; background:white"> </span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597; background:white">Hope this helps in some capacity.
</span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597; background:white"> </span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597; background:white">Best Regards,</span></p>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597; background:white"><br>
Matt</span><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#2F5597"></span></p>
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<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#1F497D"> </span></p>
<div>
<p class="x_MsoNormal"><span style="font-size:11.0pt; font-family:"Calibri",sans-serif; color:#1F497D">--
<br>
<b>Matthew T. Moneck, Ph.D.</b><br>
Executive Manager, Claire & John Bertucci Nanotechnology Laboratory<br>
Electrical and Computer Engineering | Carnegie Mellon University<br>
5000 Forbes Ave., Pittsburgh, PA 15213-3890<br>
T: 412.268.5430<br>
F: 412.268.3497<br>
<a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__www.ece.cmu.edu_&d=DwMFAg&c=ODFT-G5SujMiGrKuoJJjVg&r=viXbs6wGaGZ-o2y0LFbqZrWN_jy4Cw47zl8d3Wrr2M4&m=xcsoSqLZ1td4AHsfpW_fG71YxxRin21Y89KQILp8A30&s=yTWyjWfxzDFxrSZSFCC3jDg83rT8xIXzXQtGhcpAREQ&e=">www.ece.cmu.edu</a><br>
nanofab.ece.cmu.edu</span></p>
</div>
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<p class="x_MsoNormal"><b><span style="font-size:11.0pt; font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt; font-family:"Calibri",sans-serif">
<a href="mailto:labnetwork-bounces@mtl.mit.edu">labnetwork-bounces@mtl.mit.edu</a> [<a href="mailto:labnetwork-bounces@mtl.mit.edu">mailto:labnetwork-bounces@mtl.mit.edu</a>]
<b>On Behalf Of </b>Martin,Michael David<br>
<b>Sent:</b> Monday, March 18, 2019 2:07 PM<br>
<b>To:</b> <a href="mailto:labnetwork@mtl.mit.edu">labnetwork@mtl.mit.edu</a><br>
<b>Subject:</b> [labnetwork] CMOS Clean in a MEMS Fab Facility</span></p>
</div>
</div>
<p class="x_MsoNormal"> </p>
<div>
<p class="x_MsoNormal"><span style="font-family:"Calibri",sans-serif; color:black">Hi,
</span></p>
</div>
<div>
<p class="x_MsoNormal"><span style="font-family:"Calibri",sans-serif; color:black"> I'm trying to track down potential sources of contamination for a CMOS process we are trying to run through our predominantly MEMS fab here at U of Louisville. Really the
only pieces of equipment that are dedicated for CMOS type processes is our RCA bench, an older Technics sputterer, and our oxidation furnace (sort of, see below). So I have a few questions for those of you who have experience with this:
</span></p>
</div>
<div>
<p class="x_MsoNormal"><span style="font-family:"Calibri",sans-serif; color:black">1) For HF etch/dips is there a particular polymer type or brand we should use for our containers that are known to be free of trace metals? Can I avoid PTFE as this is super
expensive? </span></p>
</div>
<div>
<p class="x_MsoNormal"><span style="font-family:"Calibri",sans-serif; color:black">2) When you do litho do you have separate labware for developing? We currently use a Pyrex pan develop which I know is a No-No due to Na and other ions. What sort of container
does your lab use (assuming pan develop)? </span></p>
</div>
<div>
<p class="x_MsoNormal"><span style="font-family:"Calibri",sans-serif; color:black"> 2 a) Do you have a dedicated spinner for CMOS?
</span></p>
</div>
<div>
<p class="x_MsoNormal"><span style="font-family:"Calibri",sans-serif; color:black"> 2 b) Is there any danger that we are picking up contamination from the amber bottles we are temporarily storing our resists in? What about the polypropylene droppers we are
dispensing resists with? </span></p>
</div>
<div>
<p class="x_MsoNormal"><span style="font-family:"Calibri",sans-serif; color:black"> 2 c) What about resist stripping after etching? We typically use a big warm vat of NMP that is shared by all users. We can also do a plasma etch but I worry about carry over
from other folks as none of our plasma etchers are dedicated CMOS. </span></p>
</div>
<div>
<p class="x_MsoNormal"><span style="font-family:"Calibri",sans-serif; color:black">3) I presume quartz glassware works for my metal (usually aluminum) etching? Do you do regular aqua regia cleans on quartz-ware to scavenge other metals and potential contaminants?
</span></p>
</div>
<div>
<p class="x_MsoNormal"><span style="font-family:"Calibri",sans-serif; color:black">4) We gravitate to peek tipped metal tweezers. Are they okay? Do you regularly run the tips through a RCA clean?
</span></p>
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<p class="x_MsoNormal"><span style="font-family:"Calibri",sans-serif; color:black">5) Oxidation furnace: Before trying to transition to CMOS like devices the tube was used with non-RCA cleaned wafers and a pyrex bubbler. After moving to a quartz bubbler with
DI water we cleaned the 4" tube with HF. This is the one I'm really concerned about because I'm guessing that ionic contamination that might have been removed from the surface will readily diffuse back at 1000C. So should we just bite the bullet and buy
a new tube? Any vendor suggestions for a 4" Blue-M? </span></p>
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<p class="x_MsoNormal"><span style="font-family:"Calibri",sans-serif; color:black">6) Any other suggestions other than buying a dedicated CMOS tool set?
</span></p>
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<p class="x_MsoNormal"><span style="font-family:"Calibri",sans-serif; color:black"> </span></p>
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<p class="x_MsoNormal"><span style="font-family:"Calibri",sans-serif; color:black">I did find a very nice document from Stanford that has a lot of practical suggestions found here
<a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__web.stanford.edu_class_ee410_cleaning.pdf&d=DwMFAg&c=ODFT-G5SujMiGrKuoJJjVg&r=viXbs6wGaGZ-o2y0LFbqZrWN_jy4Cw47zl8d3Wrr2M4&m=xcsoSqLZ1td4AHsfpW_fG71YxxRin21Y89KQILp8A30&s=lekItA7Hi5mB01_AWgTSdp3AJDQnHLLdzAcqSCbAjWw&e=" id="LPlnk395163">
https://web.stanford.edu/class/ee410/cleaning.pdf</a> )</span></p>
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<div id="LPBorder_GTaHR0cHM6Ly93ZWIuc3RhbmZvcmQuZWR1L2NsYXNzL2VlNDEwL2NsZWFuaW5nLnBkZg.." style="margin-top:12.0pt; margin-bottom:12.0pt; max-width:800px; min-width:424px">
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<p class="x_MsoNormal"><span style=""><a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__web.stanford.edu_class_ee410_cleaning.pdf&d=DwMFAg&c=ODFT-G5SujMiGrKuoJJjVg&r=viXbs6wGaGZ-o2y0LFbqZrWN_jy4Cw47zl8d3Wrr2M4&m=xcsoSqLZ1td4AHsfpW_fG71YxxRin21Y89KQILp8A30&s=lekItA7Hi5mB01_AWgTSdp3AJDQnHLLdzAcqSCbAjWw&e=" target="_blank"><span style="text-decoration:none">Krishna
Saraswa - Stanford University</span></a></span></p>
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<div id="LPDescription778519" style="margin-right:6.0pt; margin-bottom:9.0pt; max-height:100px; overflow:hidden">
<p class="x_MsoNormal"><span style="">6 tanford University araswat 11! Cleaning - Surface Issues Contaminant • Organics – Skin oils – Resist – Polymers • Metals</span></p>
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<p class="x_MsoNormal"><span style="">web.stanford.edu</span></p>
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<p class="x_MsoNormal">Thank you in advance, </p>
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<p class="x_MsoNormal"> Michael </p>
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<p class="x_MsoNormal"> </p>
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