<div dir="ltr"><div dir="ltr"><div class="gmail_default" style="font-family:verdana,sans-serif;color:#000066"><span style="color:rgb(34,34,34);font-family:Tahoma">Dear Dr. Xuekun Lu,</span></div><div class="gmail_default" style=""><font face="Tahoma">I guess there may be a thick polymer deposition on the table (mechanical chuck). This polymer could be from C4F8. If someone used your tool for polymer depositions or if the plasma is turned on without a wafer on the mechanical chuck, </font><span style="font-family:Tahoma">this can happen. </span><span style="font-family:Tahoma"> </span></div><div class="gmail_default" style=""><font face="Tahoma"><br></font></div><div class="gmail_default" style=""><font face="Tahoma">I suggest you may want to do a mild rub on the table (chuck) using IPA+DI water and see if there is any DC bias. </font></div><div class="gmail_default" style=""><font face="Tahoma"><br></font></div><div class="gmail_default" style=""><font face="Tahoma">Thanks & best regards,</font></div><div class="gmail_default" style=""><font face="Tahoma">vamsi</font></div><div class="gmail_default" style=""><font face="Tahoma"><br></font></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Fri, Apr 5, 2019 at 5:25 AM Xuekun Lu <<a href="mailto:xklu@eng.ucsd.edu">xklu@eng.ucsd.edu</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr">Dear colleagues,<div><br></div><div>I am sorry to borrow this thread to ask this question, but it is a related question. Please let me know if I should start a separate subject.</div><div><br></div><div>We have an Oxford PlasmalabSystem 100 with ICP180. Whenever we use a insulating carrier wafer (fused silica wafer, or silicon wafer coated with thick SiO2 film), the DC bias reading would be zero. As everybody knows that this does not mean the sample is subject to zero bias, but in our case, it seems that the sample DOES subject to zero bias. The etch result will be more isotropic with very low etch rate. This is even more a problem when running SiO2 etch with CHF3/Ar plasma, because this process highly relies on DC bias (ion bombardment), we got almost no etching when using insulating carrier wafers. If we use silicon wafer as carrier, everything would be fine. For other owners of this machine, I am wondering if you have the same issue or it is just our machine. I had asked Oxford for this, but had not been able to get an explanation.</div><div><br></div><div>Any input would be greatly appreciated!</div><div><br></div><div>Thanks,</div><div>Xuekun </div><div><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Apr 4, 2019 at 9:58 AM Fabien Dauzou <<a href="mailto:fabien@edgehogtech.com" target="_blank">fabien@edgehogtech.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
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<p class="MsoNormal"><span>Hi Srinivasa,<u></u><u></u></span></p>
<p class="MsoNormal"><span><u></u> <u></u></span></p>
<p class="MsoNormal"><span>In the past we have been using alumina wafer carrier [1-2mm] to proceed with cleaning of RIE and DRIE.<u></u><u></u></span></p>
<p class="MsoNormal"><span>You can also use standard wafer with a photoresist or certain coating (SiO2, Cr…) to avoid wafer consumption. It should be fine with the helium backside cooling.<u></u><u></u></span></p>
<p class="MsoNormal"><span><u></u> <u></u></span></p>
<p class="MsoNormal"><span lang="FR">Best regards, Bien cordialement,<u></u><u></u></span></p>
<p class="MsoNormal"><span lang="FR"><u></u> <u></u></span></p>
<p class="MsoNormal"><span lang="FR">Fabien Dauzou (Jr. Eng.)<u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US">R&D Process Engineer<u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US"><a href="mailto:fabien@edgehogtech.com" target="_blank"><span style="color:rgb(5,99,193)">fabien@edgehogtech.com</span></a><u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US">Mob: 438-868-1657<u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US"><a href="https://www.edgehogtech.com/" target="_blank"><span style="color:rgb(5,99,193)">https://www.edgehogtech.com/</span></a><u></u><u></u></span></p>
<p class="MsoNormal"><img border="0" width="157" height="89" style="width: 1.6388in; height: 0.9305in;" id="gmail-m_343788791728862991m_-2899228987401812480m_8477376047344986128gmail-m_-3083859506424299423Picture_x0020_4" src="cid:169e99b319e5b16b21"><u></u><u></u></p>
<p class="MsoNormal"><span style="font-size:10pt">780 Av. Brewster, Montreal, QC, Canada, H4C 2K1<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:8pt;color:rgb(0,176,80)">Think green, before printing this email.</span><span lang="EN-US" style="font-size:8pt;color:rgb(0,176,80)"><u></u><u></u></span></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal"><span><u></u> <u></u></span></p>
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<p class="MsoNormal"><b><span lang="EN-US">From:</span></b><span lang="EN-US"> <a href="mailto:labnetwork-bounces@mtl.mit.edu" target="_blank">labnetwork-bounces@mtl.mit.edu</a> <<a href="mailto:labnetwork-bounces@mtl.mit.edu" target="_blank">labnetwork-bounces@mtl.mit.edu</a>> <b>On Behalf Of </b>Srinivasa Reddy<br>
<b>Sent:</b> April 4, 2019 1:42 AM<br>
<b>To:</b> <a href="mailto:labnetwork@mtl.mit.edu" target="_blank">labnetwork@mtl.mit.edu</a><br>
<b>Subject:</b> [labnetwork] Wafer specification requirement for RIE & DRIE cleaning recopies<u></u><u></u></span></p>
<p class="MsoNormal"><u></u> <u></u></p>
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<p class="MsoNormal">HI,<u></u><u></u></p>
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<p class="MsoNormal">I'm Srinivasa Reddy, Manger, Microfabrication Lab, Indian Institute of Technology, Madras, Chennai.<u></u><u></u></p>
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<p class="MsoNormal">This is regarding Wafers specifications for Dummy wafers for RIE & DRIE process.<u></u><u></u></p>
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<div>
<p class="MsoNormal">1. Some times we stick <b>small prices</b> to f<b>ull 4 inch wafer</b> and do the etching process.<u></u><u></u></p>
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<p class="MsoNormal">Currently we are using <b>Prime Wafers</b> ( which costly) and I'm looking to replace with Mechanical grade or Test grade wafers. <u></u><u></u></p>
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<p class="MsoNormal">2. We also do chamber cleaning runs with the wafers and this also consumes significant number of wafers. Here also want to replace the Prime wafer with Test or Mechanical grade wafer.<u></u><u></u></p>
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<p class="MsoNormal"><u></u> <u></u></p>
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<p class="MsoNormal">I've doubt about the Bending/Warping or TTV or backside roughness of the wafer and It may lead to higher helium leak rate and process may abort.<u></u><u></u></p>
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<p class="MsoNormal">Could some one throw light on this issue<u></u><u></u></p>
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<p class="MsoNormal"><u></u> <u></u></p>
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<u></u><u></u></p>
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<p class="MsoNormal">Thanks & Regards<u></u><u></u></p>
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<p class="MsoNormal">Srinivasa Reddy Kuppireddi<u></u><u></u></p>
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<p class="MsoNormal">Project Manager <u></u><u></u></p>
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<p class="MsoNormal">Center for NEMS & Nano Photonics (CNNP)<u></u><u></u></p>
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<p class="MsoNormal">ESB 225, Dept. of Electrical Engineering<u></u><u></u></p>
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<p class="MsoNormal">Indian Institute of Technology(IIT) Madras<u></u><u></u></p>
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<p class="MsoNormal">Chennai-600036, Indian<u></u><u></u></p>
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<p class="MsoNormal">+91 44 2257 5493 (O)<u></u><u></u></p>
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<p class="MsoNormal">+91 789 326 8010(M)<u></u><u></u></p>
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</blockquote></div><br clear="all"><div><br></div>-- <br><div dir="ltr" class="gmail-m_343788791728862991m_-2899228987401812480m_8477376047344986128gmail_signature"><div dir="ltr"><div><font size="2" face="Tahoma">----------------------------------------</font></div>
<font face="Tahoma"><font size="2">Dr. Xuekun Lu<br>
<br>University of California, San Diego<br>Calit2 M/C</font></font><font face="Tahoma"><font size="2">0436<br>9500 Gilman Drive<br>La Jolla, CA 92093-0436<br>
<br>For Fedex Shipping:<br>Dr. Xuekun Lu<br>University of California, San Diego<br>Atkinson Hall 5th Floor Front Desk<br>9500 Gilman Drive<br>La Jolla, CA 92093<br>
<br>Phone: (858) 246-0411<br>Fax: (858) 246-0408<br>E-mail: <a href="mailto:xklu@ucsd.edu" target="_blank">xklu@ucsd.edu</a><br>
</font><a href="https://mail.ucsd.edu/owa/redir.aspx?C=317d92da2d2640938cbc0ac31f2a741b&URL=http%3a%2f%2fnano3.calit2.net%2f" target="_blank"><font size="2">http://nano3.calit2.net/</font></a></font></div></div></div>_______________________________________________<br>labnetwork mailing list<br>
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</blockquote></div><br clear="all"><div><br></div>-- <br><div dir="ltr" class="gmail_signature"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><font style="font-family:verdana,sans-serif;color:rgb(0,0,102)" size="2"><span style="color:rgb(102,102,102)">--<br>Thanks & Best Regards,<br>-----------------<br><b><span class="gmail_default" style="font-family:verdana,sans-serif;color:rgb(0,0,102)"> Dr. </span>N.P.Vamsi Krishna</b></span><br></font><span style="color:rgb(0,0,102);font-family:verdana,sans-serif">3D Heterogeneous Integration and System Scaling Lab,</span><font style="font-family:verdana,sans-serif;color:rgb(0,0,102)" size="2"><br></font></div><div dir="ltr"><font style="font-family:verdana,sans-serif;color:rgb(0,0,102)" size="2"><span>Center for Nano Science and Engineering (CeNSE),<br>Indian Institute of Science(IISc), Banga<font size="2">lore.</font><br><font size="2">INDIA</font></span>-</font><font style="font-family:verdana,sans-serif;color:rgb(0,0,102)" size="2"><span>560012</span></font></div></div></div></div></div></div></div>