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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">I think this is a summary of what others have said, but to recap from my experience.
<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">Rule out matching issues first, if your process log shows a good match with low reflected power then you are generally good. Can be
hard to see sometimes in the fast switching steps of DRIE so make sure you log interval is sufficiently fast for good resolution.
<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">Once that is sorted grassing is nearly always a result of poor C:F matching in process relative to the active material areas exposed
to the plasma. Broadly speaking Si is a F sink, resist will contribute C back to the plasma, SiO2 is an F sink but not as much as C and will contribute O back to the plasma which can reduce C density. Very hand wavy but broadly true.
<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">If you see black silicon then the surface has roughened. If the surface is roughened then logically you have not cleared the polymer
from it sufficiently before the isotropic SF6 etch step. So to combat this you need a shorter C4F8 dep step or a longer anisotropic SF6 etch to ensure polymer removal from planar surfaces. A 2<sup>nd</sup> hypothesis is that you also have insufficient SF6
flow in the isotropic etch step for your exposed Si area but I find this less likely. Still worth investigating.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">3<sup>rd</sup> hypothesis – another user of the tool has been using excessive vacuum oil or involatile mask materials which have then
redeposited from chamber walls to micromask the black Si areas. An Al mask would be a classic via involatile AlF formation. This is a problem for us in shared use non-DRIE ICP tools occasionally. Not much you can do apart from wet clean/plasma clean the chamber
until problem goes away. If you are running similar chip sizes on Si wafers before with no issues perhaps consider this idea more.
<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">When we train users on etch tools we always mention to them the issue of processes that are sensitive to exposed material areas, and
C:F etch processes are a classic. A lot of our users are running what I call ‘mixed Boschs’ which is a constant flow of SF6:C4F8 intended to tune sidewall angle on standard ICP tools. When it works, it works very well. But if they upscale from chip to wafer,
or change mask pattern, or change carrier wafer material the performance will shift and DRIE is the same. We try to educate them in this as early as possible to save pain. Despite the extra work involved if they intend to upscale from chip to wafer then it
is best to start with a carrier wafer that mimics the final wafer as much as possible, which usually involves a resist spun carrier wafer. More work initially but saves time in the long run.
<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">Once I saw a user perfect a Ta2O5 C4F8/O2 etch on a 20mm chip, C4F8/O2 process, excellent sidewalls. He was very surprised when he
upscaled to a 4” Tas2O5 wafer (still on 6” Si carrier) and the etch shifted from etch to deposition and he ended up with a layer of CF polymer all over his device wafer. Since then, we try to avoid this with early education!<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">We don’t allow chips in our DRIE anymore, it was too much of a problem relating to issues like this, chamber contamination with vacuum
oil affecting other users processes etc. It is supposed to be a clean Si/Si dielectric/resist only tool so best to not allow in<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">Can’t really comment on the recipes being as all tools have their own personalities, we run a Plasmatherm Versaline.
<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">Regards, Owain<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US"><o:p></o:p></span></p>
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<p class="MsoNormal"><b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif"> labnetwork <labnetwork-bounces@mtl.mit.edu>
<b>On Behalf Of </b>Shepard, Jeremiah J<br>
<b>Sent:</b> 22 July 2021 14:52<br>
<b>To:</b> labnetwork@mtl.mit.edu<br>
<b>Subject:</b> [labnetwork] Fw: ICP STS ASE Issue<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<div style="border:solid #8D3970 1.0pt;padding:9.0pt 9.0pt 9.0pt 9.0pt">
<p class="MsoNormal" style="line-height:16.5pt;background:#F7F9FA"><strong><span style="font-size:10.5pt;font-family:"Calibri",sans-serif;color:#8D3970">CAUTION:</span></strong><span style="font-size:10.5pt;font-family:"Calibri",sans-serif;color:#8D3970"> This
e-mail originated outside the University of Southampton. <o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black">Ok so here are my process parameters:<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black">#1 Recipe (this is the "standard recipe" for users)<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black">10 second Etch / 10 second Dep<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black">30 mTorr Etch pressure / 50 mTorr Dep pressure<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black">1000 watts Etch coil / 1000 watts Dep coil<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black">10 watts Etch Platen Hf / 0 watts Dep Platen Hf<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black">250 sccm Sf6 with 30 sccm O2 Etch gas / 100 sccm C4F8 Dep gas<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black">#2 Recipe (This is not standard but is still producing grass)<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black">5 second Etch / 5 second Dep<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black">25 mTorr Etch pressure / 25 mTorr Dep pressure<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black">450 watts Etch coil / 800 watts Dep coil<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black">13 watts Etch Platen Hf / 0 watts Dep Platen Hf<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black">85 sccm Sf6 with 8.5 O2 Etch gas / 130 sccm C4F8 Dep gas<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black;background:white">Etch and tune caps are Auto tuned so I'm not sure how to adjust these if possible.</span><span style="font-family:"Calibri",sans-serif;color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black;background:white">Thanks,</span><span style="font-family:"Calibri",sans-serif;color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black;background:white">Jerry</span><span style="font-family:"Calibri",sans-serif;color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black"> Bruce Tolleson <<a href="mailto:betemc@rit.edu">betemc@rit.edu</a>><br>
<b>Sent:</b> Thursday, July 22, 2021 7:58 AM<br>
<b>To:</b> Shepard, Jeremiah J <<a href="mailto:jshepar@purdue.edu">jshepar@purdue.edu</a>><br>
<b>Subject:</b> RE: ICP STS ASE Issue</span> <o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="xmsonormal"><span lang="EN-US">This is DRIE? Is the carrier made of Silicon with no capping layer of metal (this is what it appears to be). If that is the case, there is the (big) problem: DRIE is extremely dependent on exposed silicon area, so having
a massive amount of silicon available would certainly cause strange things like this. <o:p></o:p></span></p>
<p class="xmsonormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"> </span><span lang="EN-US"><o:p></o:p></span></p>
<p class="xmsonormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"> </span><span lang="EN-US"><o:p></o:p></span></p>
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<p class="xmsonormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Bruce E. Tolleson</span><span lang="EN-US"><o:p></o:p></span></p>
<p class="xmsonormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Rochester Institute of Technology</span><span lang="EN-US"><o:p></o:p></span></p>
<p class="xmsonormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">82 Lomb Memorial Drive, Bldg 17-2627</span><span lang="EN-US"><o:p></o:p></span></p>
<p class="xmsonormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Rochester, NY 14623-5604</span><span lang="EN-US"><o:p></o:p></span></p>
<p class="xmsonormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">(585) 478-3836</span><span lang="EN-US"><o:p></o:p></span></p>
<p class="xmsonormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:navy"><img border="0" width="90" height="60" style="width:.9375in;height:.625in" id="x_Picture_x0020_1" src="cid:image001.jpg@01D77FAF.AF1089E0" alt="http://www.rit.edu/~962www/logos/tiger_walking_rit_color.jpg"></span><span lang="EN-US"><o:p></o:p></span></p>
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<p class="xmsonormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"> </span><span lang="EN-US"><o:p></o:p></span></p>
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<p class="xmsonormal"><b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif"> labnetwork <<a href="mailto:labnetwork-bounces@mtl.mit.edu">labnetwork-bounces@mtl.mit.edu</a>>
<b>On Behalf Of </b>Shepard, Jeremiah J<br>
<b>Sent:</b> Wednesday, July 21, 2021 9:44 AM<br>
<b>To:</b> <a href="mailto:labnetwork@mtl.mit.edu">labnetwork@mtl.mit.edu</a><br>
<b>Subject:</b> [labnetwork] ICP STS ASE Issue</span><span lang="EN-US"><o:p></o:p></span></p>
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<p class="xmsonormal"><span lang="EN-US"> <o:p></o:p></span></p>
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<p class="xmsonormal"><span lang="EN-US" style="font-family:"Calibri",sans-serif;color:black">I am having some trouble determining what this issue is? We have found a bad capacitor in the matching network, and replaced that, thought all was good but now we
face this issue. </span><span lang="EN-US"><o:p></o:p></span></p>
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<p class="xmsonormal"><span lang="EN-US" style="font-family:"Calibri",sans-serif;color:black"> </span><span lang="EN-US"><o:p></o:p></span></p>
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<p class="xmsonormal"><span lang="EN-US" style="font-family:"Calibri",sans-serif;color:black">Now I am having trouble with grass formation on student sample. Anyone know where to look for this kind of thing? Is it just sample recipe or something else perhaps?
Any thoughts are appreciated! Also unsure of what's going on with the carrier wafer around the sample...?</span><span lang="EN-US"><o:p></o:p></span></p>
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<p class="xmsonormal"><span lang="EN-US" style="font-family:"Calibri",sans-serif;color:black"> </span><span lang="EN-US"><o:p></o:p></span></p>
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<p class="xmsonormal"><span lang="EN-US" style="font-family:"Calibri",sans-serif;color:black">Thanks,</span><span lang="EN-US"><o:p></o:p></span></p>
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<p class="xmsonormal"><span lang="EN-US" style="font-family:"Calibri",sans-serif;color:black">Jerry Shepard</span><span lang="EN-US"><o:p></o:p></span></p>
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<p class="xmsonormal"><span lang="EN-US" style="font-family:"Calibri",sans-serif;color:black"> </span><span lang="EN-US"><o:p></o:p></span></p>
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<p class="xmsonormal"><span lang="EN-US" style="font-family:"Calibri",sans-serif;color:black"><img border="0" width="694" height="576" style="width:7.2291in;height:6.0in" id="x__x005f_x0000_i1025" src="cid:image002.png@01D77FAF.AF1089E0"></span><span lang="EN-US"><o:p></o:p></span></p>
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