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--></style></head><body lang="EN-US" link="#0563C1" vlink="#954F72"><div class="WordSection1"><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Hi Long,</span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"> </span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">The PR approach can work, but we have had problems with wafers coming apart during the etch and subsequently changing the heat transfer properties.  We now use 150C heat release tape from Revalpha for bonding of full 4” wafers or large wafer pieces.  We have been able to achieve up to 7-8hrs of etching in our STS Multiplex without causing activation of the heat release surface.  However, the trick is to ensure you apply the tape with no bubbles.  Subsequent debonding of the wafers can then be done using the standard release temperature for 150C tape.  </span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"> </span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Best Regards,<br><br></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Matt</span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"> </span></p><div><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">--</span></p><p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Matthew T. Moneck, Ph.D</span></b></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Executive Director, Claire & John Bertucci Nanotechnology Laboratory</span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Electrical & Computer Engineering | Carnegie Mellon University</span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">5000 Forbes Avenue, Pittsburgh, PA 15213-3890</span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Phone:  412-268-5430</span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><a href="http://www.ece.cmu.edu/">ece.cmu.edu</a> </span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><a href="http://www.nanofab.ece.cmu.edu/">nanofab.ece.cmu.edu</a> </span></p></div><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"> </span></p><div><div style="border:none;border-top:solid #e1e1e1 1.0pt;padding:3.0pt 0in 0in 0in"><p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> labnetwork <<a href="mailto:labnetwork-bounces@mtl.mit.edu">labnetwork-bounces@mtl.mit.edu</a>> <b>On Behalf Of </b>Chang, Long<br><b>Sent:</b> Monday, April 11, 2022 5:10 PM<br><b>To:</b> <a href="mailto:labnetwork@mtl.mit.edu">labnetwork@mtl.mit.edu</a><br><b>Subject:</b> [labnetwork] RIE through Silicon</span></p></div></div><p class="MsoNormal"> </p><p class="MsoNormal">Hi Guys, </p><div><p class="MsoNormal"> </p></div><div><p class="MsoNormal">I have an Oxford RIE with backside Helium. I want to etch through the silicon wafer (380um thick). The largest pattern is a 1mm diameter circle. My plan is to ride the 4” sample wafer on a 4" carrier wafer with PR. Does anyone have a good solution to this problem?</p></div><div><p class="MsoNormal"> </p></div><div><p class="MsoNormal">Thanks,</p><div><div><p class="MsoNormal"><span style="color:black">Long</span></p></div></div><p class="MsoNormal"> </p></div></div></body></html>