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<p>We use pulsed power supplies with forward and reverse current
capabilities, so you can tune the grain size and growth better
than with straight power...it takes some development time for sure
to get it right. (electrochemistry is black magic!) Plating off
of Pt is usually pretty good assuming you have a nice contiguous
film that you can solidly contact in your fixturing. I'd also
advise to try and go slowly and not try for a plating speed
record... <br>
</p>
<div class="moz-cite-prefix">On 2/27/25 16:07, Artner, Diane M
wrote:<br>
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<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Aptos",serif">For
the electroplating of vias with Pt seed, have you seen poor
nucleation, basically large grain growth vs uniform small
grain size bottom up fill?
<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Aptos",serif"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">
labnetwork <a class="moz-txt-link-rfc2396E" href="mailto:labnetwork-bounces@mtl.mit.edu"><labnetwork-bounces@mtl.mit.edu></a>
<b>On Behalf Of </b>Christopher Alpha<br>
<b>Sent:</b> Thursday, February 27, 2025 10:41 AM<br>
<b>To:</b> <a class="moz-txt-link-abbreviated" href="mailto:labnetwork@mtl.mit.edu">labnetwork@mtl.mit.edu</a><br>
<b>Subject:</b> Re: [labnetwork] Copper Through-Glass
Vias on fused silica<o:p></o:p></span></p>
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<pre><span style="color:black">
</span><o:p></o:p></pre>
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<div>
<p>Hi Folks,<o:p></o:p></p>
<p><o:p> </o:p></p>
<p>(RE: Mac's comments)<o:p></o:p></p>
<p><o:p> </o:p></p>
<p>We often do Pt seed layers by ALD for via Cu electroplating
fills...you can get voids though depending on aspect ratio
and how you drive the plating. If a a hollow wire is OK
this is fine to do in this fashion. <o:p></o:p></p>
<p><o:p> </o:p></p>
<p>If you want a full solid fill we have done Au or Pt sputter
on only one side of a very high aspect ratio via and
basically try to sputter the hole mostly if not fully closed
and use a plating fixture that makes contact on the back
side with the Pt seed, leaving the other side exposed in the
plating bath, then you can get a nice fill by plating from
the bottom of the via up. Overtop the via/wafer's surface,
and CMP everything clean and flat (remove seed either
selectively with wet chemistry if possible or CMP that off
too).<o:p></o:p></p>
<p><o:p> </o:p></p>
<p>Your mileage may vary...electroplating is a dark art.<o:p></o:p></p>
<p><o:p> </o:p></p>
<p>Best,<o:p></o:p></p>
<p>C<o:p></o:p></p>
<pre>-- <o:p></o:p></pre>
<pre>Christopher Alpha<o:p></o:p></pre>
<pre>User Program Manager<o:p></o:p></pre>
<pre>Cornell Nanoscale Facility<o:p></o:p></pre>
<pre>Cornell University<o:p></o:p></pre>
<pre>250 Duffield Hall<o:p></o:p></pre>
<pre>343 Campus Rd<o:p></o:p></pre>
<pre>Ithaca, NY 14853<o:p></o:p></pre>
<pre>tel (607)254-4913<o:p></o:p></pre>
<pre><o:p> </o:p></pre>
<pre>Any email from me will always really be from me without any AI "assistance"<o:p></o:p></pre>
<p> <o:p></o:p></p>
<div>
<p class="MsoNormal">On 2/26/25 13:04, Hathaway, Malcolm R
wrote:<o:p></o:p></p>
</div>
<blockquote style="margin-top:5.0pt;margin-bottom:5.0pt">
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif">Hi Larry,<o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif"><o:p> </o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif">As it
happens, Cu is not an established ALD process yet
(that I am aware of).<o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif"><o:p> </o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif">Pt is
common, but for your purposes (filling a 20um diameter
hole) Pt would likely too expensive. In fact, ALD is
probably not a viable option because you will need a
layer slightly thicker than the radius of the hole
(i.e. 10 um) and ALD of almost anything in a 10um
thickness will take 2-3 weeks (at least in our
systems). We tend to speak of dep thickness/cycle
(~1A) because to speak of rate in thickness/min is too
embarrassing!<o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif"><o:p> </o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif">Which is
to say, ALD is slow. <o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif"><o:p> </o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif">Typical
films are under 200nm.<o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif"><o:p> </o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif">Material-wise,
Pt, Ru, and some other conductors are available, but
they tend to be on the (even) slower side. Some newer
systems will get cycle times down to achieve 20-30
cy/min, but still nothing approaching CVD growth
rates.<o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif"><o:p> </o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif">A Pt liner
(or other conductive material) with Cu electroplating
is much closer to a standard process for this sort of
thing. And if you wanted to get fancy you could even
consider selective W CVD, but that would require a bit
of process development.<o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif"><o:p> </o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif">I'm happy
to chat about this off-line if you like. Hopefully
others with proper electroplating experience will
chime in shortly.<o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif"><o:p> </o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif"><o:p> </o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif">Mac<o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif">Harvard
CNS<o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif"><o:p> </o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span
style="font-family:"Aptos",serif"><o:p> </o:p></span></p>
</div>
<div class="MsoNormal" align="center"
style="text-align:center">
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</div>
<div id="divRplyFwdMsg">
<p class="MsoNormal"><b><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif"> labnetwork
<a href="mailto:labnetwork-bounces@mtl.mit.edu"
moz-do-not-send="true"><labnetwork-bounces@mtl.mit.edu></a>
on behalf of Hess, Larry A. (GSFC-5530)
<a href="mailto:larry.hess-1@nasa.gov"
moz-do-not-send="true"><larry.hess-1@nasa.gov></a><br>
<b>Sent:</b> Wednesday, February 26, 2025 9:36 AM<br>
<b>To:</b> <a href="mailto:labnetwork@mtl.mit.edu"
moz-do-not-send="true" class="moz-txt-link-freetext">labnetwork@mtl.mit.edu</a>
<a href="mailto:labnetwork@mtl.mit.edu"
moz-do-not-send="true">
<labnetwork@mtl.mit.edu></a><br>
<b>Subject:</b> [labnetwork] Copper Through-Glass Vias
on fused silica</span> <o:p>
</o:p></p>
<div>
<p class="MsoNormal"> <o:p></o:p></p>
</div>
</div>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">Hi,<o:p></o:p></span></p>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">I am
looking for a (hopefully established) source to deposit
ALD copper on Though-Glass Vias.<o:p></o:p></span></p>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">The
vias are about 20um in diameter with an aspect ratio of
about 10:1.<o:p></o:p></span></p>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">I
would also consider Cu electroplating( after an
appropriate ALD adhesion/base layer), but I’m not sure
how feasible that is given the via diameter and aspect
ratio.<o:p></o:p></span></p>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif"> <o:p></o:p></span></p>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">Thanks
for your help!<o:p></o:p></span></p>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif"> <o:p></o:p></span></p>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">Larry<o:p></o:p></span></p>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif"> <o:p></o:p></span></p>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">Larry
A. Hess, PhD<o:p></o:p></span></p>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">NASA<o:p></o:p></span></p>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">Goddard
Space Flight Center<o:p></o:p></span></p>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">8800
Greenbelt Road<o:p></o:p></span></p>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">Code
553, Detector Systems Branch<o:p></o:p></span></p>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">Building
11, Room E011<o:p></o:p></span></p>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">Greenbelt,
MD 20771<o:p></o:p></span></p>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">301-286-0259
(P)<o:p></o:p></span></p>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif">301-286-1672
(F)<o:p></o:p></span></p>
<p><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif"> <o:p></o:p></span></p>
<p class="MsoNormal"><br>
<br>
<o:p></o:p></p>
<pre>_______________________________________________<o:p></o:p></pre>
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<pre class="moz-signature" cols="72">--
Christopher Alpha
User Program Manager
Cornell Nanoscale Facility
Cornell University
250 Duffield Hall
343 Campus Rd
Ithaca, NY 14853
tel (607)254-4913
Any email from me will always really be from me without any AI "assistance"</pre>
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