[labnetwork] Chamber Cleaning With Gold Contamination

[Kamal Yadav]

Dear Mary,

Your response is extremely helpful. So Nitride coat in a gold chamber,
prior to device process in which gold is a threat can be done. I have
emailed you requesting more details on the steps followed to prove this.

For the anti-contamination efforts here at IIT Bombay, last year, I have
processed clean samples in different equipment, at different stages. New,
RCA cleaned, processed without gas/etc. Followed by SR-TXRF. But
the synchrotron based TXRF set up is in non-clean room, so after collecting
data from different equipment, I paused a bit cauz not sure if results
would be reliable.

But samples from gold contaminated, For Ex: Ti coated sample in gold
contaminated clearly shows peaks of Au, Zn, Cu at TXRF, while these peaks
are absent in non processed wafers or RCA cleaned wafers. In fact the
ICPCVD I am talking about also does not show any metal peaks for a oxide
coated sample in the ICPCVD, while gold pads are allowed in that equipment
parallely.

I am having little difficulty in quantifying the TXRF results mostly
because standards are needed to made in house and in class 10 or so
cleanroom, and our SR-TXRF is also situated in non clean room. I am trying
to figure out if our TXRF set up could lead to some reasonable conclusion
in the E10/E11 atoms/sq. cm. Metal contaminants could be minimal in non
clean room area and may be non clean room works.

This should help in structuring the anti contamination policy in more
optimized way, in fact that was the idea when we started this activity. But
it will take sometime.

Thanks a lot!



On Tue, Jun 9, 2015 at 12:09 AM, Mary Tang <mtang at stanford.edu> wrote:

>  Hi Kamal --
>
> At Stanford, we've been trying to evolve a materials policy that is more
> accommodating of non-CMOS processing. Even our most die-hard electronics
> researchers are demanding more flexible processing policies. We try to take
> special processing requests on a case-by-case basis with the goal of
> evolving our policies. The 3-tier system we have of clean (front end CMOS),
> semiclean (backend CMOS) and gold (catch all for everything else, with
> different classes of "gold") has served us well for many years, but is
> overly simplistic. We have certainly stretched the definitions when it
> comes to Litho, for example, where we don't have dedicated clean, semiclean
> or gold tools. The approach we are trying to take now is to assess where
> the real transfer risks are (i.e., wafer handling, volatility, ion
> bombardment, etc.) and what kind of engineering controls might mitigate
> them. In fact, this has been the underlying rationale for our Litho policy
> -- contamination risk is minimized because there will always be wet cleans
> before wafers undergo any high temp processing steps.
>
> But back to your question. Our ICP PECVD system is defined as a "flexible"
> or "all" system, which means that it can be used for CMOS-clean processing,
> but also for processes that might otherwise be classified as "gold" in our
> old nomenclature. By default, it is non-CMOS, but can be considered "clean"
> once a short plasma clean and coat process is performed. The rationale is
> that any potentially contaminated films previously deposited are removed
> with the plasma clean and any non-volatiles are covered up by the nitride
> precoat process. It is also the responsibility of the user to perform this
> clean and coat if he/she wants a CMOS-compatible process. This doesn't mean
> that everything can be processed in this system, but would not currently
> exclude wafers with gold pads.
>
> Dr. Jim McVittie, our resident expert in many areas, especially plasma
> processing, has described an experiment in which he placed a gold sample in
> a PECVD system (our legacy STS dual frequency, non-ICP, dep system). With
> an Ar plasma, he found gold deposited on an adjacent sample (analyzed by
> TXRF). After doing a plasma clean and nitride coat, gold was no longer
> detectable.  Argon sputter probably presents the worst-case situation for
> carry-over -- most processes would be deposition-only so that gold would be
> exposed to plasma for minimal time.  This result makes us reasonably
> confident that our PECVD policy is not damaging to the typical electronic
> devices processed in our lab.
>
> We are also trying to evolve our policy with regard to ICP etchers.  If
> you or anyone else has guidelines that accommodate more materials but
> without significant risk to CMOS devices, I'd really like to learn more.
>
> Thanks,
>
> Mary
>
>
> --
> Mary X. Tang, Ph.D.
> Stanford Nanofabrication Facility
> Paul G. Allen Bldg 141, Mail Code 4070
> Stanford, CA  94305
> (650)723-9980
> mtang at stanford.edu
> http://snf.stanford.edu
>
>
>
>
> On 6/5/2015 2:33 AM, Kamal Yadav wrote:
>
> Dear All,
>
>  Though may not make much sense, but would wanted to know if there are
> any successful cleaning procedures for chamber to remove affect of gold
> usage/contamination in that chamber.
>
>  We want to use the chamber with gold pads exposed to the plasma, but at
> the same time, need to allow those whose devices may get affected from gold
> [in CMOS]. Any intermediate cleaning/deposition that could significantly
> (?) reduce the affect.
>
>  Our chamber [ICPCVD] has been used [5+ years] with gold pads [exposed to
> plasma] and so far other groups have not reported any issues with their
> devices, so its working out fine till now.
>
>  But we want to take precautionary measures if any.
>
>  Thanks a lot!
>
>  --
>     Thanks,
>  Kamal Yadav
> Sr. Process Technologist
> Electrical Engineering
> IIT Bombay
> Mobile: 7506144798
>
>
> _______________________________________________
> labnetwork mailing listlabnetwork at mtl.mit.eduhttps://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork
>
>
>


-- 
Thanks,
Kamal Yadav
Sr. Process Technologist
Electrical Engineering
IIT Bombay
Mobile: 7506144798
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