[labnetwork] Oxford ICP helium backside cooling performance

[smitha nair]

Hello Vincent,

We have two Oxford ICP RIE tools (No cryo cooling).

On both the tools we face issues with the Helium leak. Most of our users
have smaller sample sizes (manually cut), so we use cool grease to stick
them on the carrier wafer. The helium flow range acceptable is < 8sccm in
these tools and we do not accept anything beyond 10sccm. We address the
issue by an open chamber clean as most of the times we end up having cool
grease on the chuck.  Also if carrier wafer edges are rough or pin holes
present, leak is high and we would change the carrier wafer.

As you mentioned, is it possible to share the dwg file we could also give a
try with quartz wafers.

It would be great to know if these issues are more common to Oxford tool or
is it general?

Regards

Smitha Nair
Technology Manager
National Nanofabrication Centre (NNFC),
Centre for Nano Science and Engineering (CeNSE),
Indian Institute of  Science (IISc),
Bangalore-560012.






On Sat, Feb 17, 2018 at 2:18 AM, Luciani, Vincent (Fed) <
Vincent.Luciani at nist.gov> wrote:

> Hello All,
>
>
>
> We have 2 Oxford Plasmalab 100 ICP etch tools that are heavily used.  100
> mm wafers are the most popular.  I am sure I discussed with many of you the
> trials and tribulations about these tools.  My question is about a yur
> experiences and lessons learned with regard to keeping the helium leak rate
> from underneath the wafer under control.  I am trying to get a general idea
> of what is typical and how we are doing compared to that.  We have several
> users that utilize the cryonic etching capability of our tools so the
> helium cooling is very important.  For those using the tool at -100 C, we
> find that 8 sccm is too high and users request repair.  We generally try to
> keep the leak rate < 5 sccm at all time but find this difficult to do with
> the variety of substrates and etch recipes.  We made some progress by
> ordering  specially made quartz discs with a cutout for the wafer flat for
> better wafer positioning.  I am happy to share the dwg if anyone would like
> it.
>
>
>
> What is your experience?  What leak rate do you find tolerable and at what
> leak rate do you shut the tool down.  Any tricks you can share?
>
>
>
>
>
> Thanks,
>
> Vince
>
>
>
>
>
> Vincent K. Luciani
>
> NanoFab Manager
>
> Center for Nanoscale Science and Technology <http://www.cnst.nist.gov/>
>
> National Institute of Standards and Technology
>
> 100 Bureau Drive, MS 6201
>
> Gaithersburg, MD 20899-6200 USA
>
> +1-301-975-2886
>
>
>
>
>
>
>
>
>
>
>
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