[labnetwork] ICP STS ASE Issue

Fri Jul 23 05:47:52 EDT 2021

I think this is a summary of what others have said, but to recap from my experience.

Rule out matching issues first, if your process log shows a good match with low reflected power then you are generally good. Can be hard to see sometimes in the fast switching steps of DRIE so make sure you log interval is sufficiently fast for good resolution.

Once that is sorted grassing is nearly always a result of poor C:F matching in process relative to the active material areas exposed to the plasma. Broadly speaking Si is a F sink, resist will contribute C back to the plasma, SiO2 is an F sink but not as much as C and will contribute O back to the plasma which can reduce C density. Very hand wavy but broadly true.

If you see black silicon then the surface has roughened. If the surface is roughened then logically you have not cleared the polymer from it sufficiently before the isotropic SF6 etch step. So to combat this you need a shorter C4F8 dep step or a longer anisotropic SF6 etch to ensure polymer removal from planar surfaces. A 2nd hypothesis is that you also have insufficient SF6 flow in the isotropic etch step for your exposed Si area but I find this less likely. Still worth investigating.

3rd hypothesis - another user of the tool has been using excessive vacuum oil or involatile mask materials which have then redeposited from chamber walls to micromask the black Si areas. An Al mask would be a classic via involatile AlF formation. This is a problem for us in shared use non-DRIE ICP tools occasionally. Not much you can do apart from wet clean/plasma clean the chamber until problem goes away. If you are running similar chip sizes on Si wafers before with no issues perhaps consider this idea more.

When we train users on etch tools we always mention to them the issue of processes that are sensitive to exposed material areas, and C:F etch processes are a classic. A lot of our users are running what I call 'mixed Boschs' which is a constant flow of SF6:C4F8 intended to tune sidewall angle on standard ICP tools. When it works, it works very well. But if they upscale from chip to wafer, or change mask pattern, or change carrier wafer material the performance will shift and DRIE is the same. We try to educate them in this as early as possible to save pain. Despite the extra work involved if they intend to upscale from chip to wafer then it is best to start with a carrier wafer that mimics the final wafer as much as possible, which usually involves a resist spun carrier wafer. More work initially but saves time in the long run.

Once I saw a user perfect a Ta2O5 C4F8/O2 etch on a 20mm chip, C4F8/O2 process, excellent sidewalls. He was very surprised when he upscaled to a 4" Tas2O5 wafer (still on 6" Si carrier) and the etch shifted from etch to deposition and he ended up with a layer of CF polymer all over his device wafer. Since then, we try to avoid this with early education!

We don't allow chips in our DRIE anymore, it was too much of a problem relating to issues like this, chamber contamination with vacuum oil affecting other users processes etc. It is supposed to be a clean Si/Si dielectric/resist only tool so best to not allow in

Can't really comment on the recipes being as all tools have their own personalities, we run a Plasmatherm Versaline.

Regards, Owain
From: labnetwork <labnetwork-bounces at mtl.mit.edu> On Behalf Of Shepard, Jeremiah J
Sent: 22 July 2021 14:52
To: labnetwork at mtl.mit.edu
Subject: [labnetwork] Fw: ICP STS ASE Issue

CAUTION: This e-mail originated outside the University of Southampton.
Ok so here are my process parameters:

#1 Recipe (this is the "standard recipe" for users)
10 second Etch / 10 second Dep
30 mTorr Etch pressure / 50 mTorr Dep pressure
1000 watts Etch coil / 1000 watts Dep coil
10 watts Etch Platen Hf / 0 watts Dep Platen Hf
250 sccm Sf6 with 30 sccm O2 Etch gas / 100 sccm C4F8 Dep gas

#2 Recipe (This is not standard but is still producing grass)
5 second Etch / 5 second Dep
25 mTorr Etch pressure / 25 mTorr Dep pressure
450 watts Etch coil / 800 watts Dep coil
13 watts Etch Platen Hf / 0 watts Dep Platen Hf
85 sccm Sf6 with 8.5 O2 Etch gas / 130 sccm C4F8 Dep gas

Etch and tune caps are Auto tuned so I'm not sure how to adjust these if possible.

Thanks,
Jerry
________________________________
From: Bruce Tolleson <betemc at rit.edu<mailto:betemc at rit.edu>>
Sent: Thursday, July 22, 2021 7:58 AM
To: Shepard, Jeremiah J <jshepar at purdue.edu<mailto:jshepar at purdue.edu>>
Subject: RE: ICP STS ASE Issue

This is DRIE? Is the carrier made of Silicon with no capping layer of metal (this is what it appears to be). If that is the case, there is the  (big) problem: DRIE is extremely dependent on exposed silicon area, so having a massive amount of silicon available would certainly cause strange things like this.

Bruce E. Tolleson

Rochester Institute of Technology

82  Lomb Memorial Drive, Bldg 17-2627

Rochester, NY 14623-5604

(585) 478-3836

[http://www.rit.edu/~962www/logos/tiger_walking_rit_color.jpg]

From: labnetwork <labnetwork-bounces at mtl.mit.edu<mailto:labnetwork-bounces at mtl.mit.edu>> On Behalf Of Shepard, Jeremiah J
Sent: Wednesday, July 21, 2021 9:44 AM
To: labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu>
Subject: [labnetwork] ICP STS ASE Issue

I am having some trouble determining what this issue is? We have found a bad capacitor in the matching network, and replaced that, thought all was good but now we face this issue.

Now I am having trouble with grass formation on student sample. Anyone know where to look for this kind of thing? Is it just sample recipe or something else perhaps? Any thoughts are appreciated! Also unsure of what's going on with the carrier wafer around the sample...?

Thanks,

Jerry Shepard

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