[labnetwork] RIE through Silicon

Kamal Yadav kamal.yadav at gmail.com
Tue Apr 12 12:12:11 EDT 2022


Hi Long,

Your PR will mostly char/ or burn, so cool grease is recommended but when
you do a through silicon via, you may be exposing the cool grease to plasma
and I am not sure what kind of damage it will bring to the devices/chamber.
Of course exposing plasma to photoresist (if that works) is fine. Thanks

On Tue, Apr 12, 2022 at 9:07 AM Hollingshead, Dave <hollingshead.19 at osu.edu>
wrote:

> Hi Long,
>
>
>
> We do this routinely with our DRIE system. As Jer mentioned, we typically
> use small drops of santovac 5 oil to adhere the two wafers together to
> provide thermal conduction. In our case we see etch rate changes or PR
> “burning” without a good thermal conductor between the samples.
>
>
>
> -Dave
>
>
>
> *From:* labnetwork <labnetwork-bounces at mtl.mit.edu> * On Behalf Of *Jeremy
> Upham
> *Sent:* Monday, April 11, 2022 23:08
> *Cc:* labnetwork at mtl.mit.edu
> *Subject:* Re: [labnetwork] RIE through Silicon
>
>
>
> I think your plan could work, so I'm not sure that I see the problem In my
> experience the carbon in the PR can contribute to the plasma chemistry and
> affect the etch, so I tend to use vacuum grease as a thermally conducting
> binder between
>
> I think your plan could work, so I'm not sure that I see the problem
>
>
>
> In my experience the carbon in the PR can contribute to the plasma
> chemistry and affect the etch, so I tend to use vacuum grease as a
> thermally conducting binder between the etched sample and the backing wafer
> instead. Though your system may well work for your recipe.
>
>
>
> Hope that helps,
>
>
>
> Jer Upham PhD
> Senior Lab Manager / Research Scientist
> Quantum Photonics Group
> University of Ottawa
> Tel.: 1 (613) 562-5800 ext 7325
>
>
>
>
>
> On Mon, Apr 11, 2022 at 6:54 PM Chang, Long <lvchang at central.uh.edu>
> wrote:
>
> *Attention : courriel externe | external email*
>
> Hi Guys,
>
>
>
> I have an Oxford RIE with backside Helium. I want to etch through the
> silicon wafer (380um thick). The largest pattern is a 1mm diameter circle.
> My plan is to ride the 4” sample wafer on a 4" carrier wafer with PR. Does
> anyone have a good solution to this problem?
>
>
>
> Thanks,
>
> Long
>
>
>
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-- 
Thanks,
Kamal
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