[labnetwork] Need help with RIE process

[Noah Clay]

Rick,

Are you running a lower power Ar plasma before/while de-chucking?  Have a look at this:

http://www.google.com/patents/US20110151669 <http://www.google.com/patents/US20110151669>

To summarize, here’s a cut-and-paste from the patent:

As part of the de-chuck process, an argon de-chuck is performed, wherein argon is introduced into chamber 42 and a radio frequency (RF) power, for example, about 400 watts, is applied to ionize argon and generate argon plasma. The RF energy may be applied for about 10 seconds. It is expected that by applying the argon plasma, the accumulated charges built up in wafer 100 are at least partially neutralized. The argon de-chuck is part of the de-chuck process because it also has the effect of releasing wafer 100.

During or after the period when the argon plasma is in chamber 42, a reverse de-chuck voltage is applied to ESC 16 to de-chuck (release) wafer 100. In an embodiment, the reverse de-chuck voltage (referred to as a high reverse de-chuck voltage hereinafter) is between about −650V and about −975V. Experiments have found that, advantageously, by limiting the reverse de-chuck voltage in this range, the JTAG failure that may occur to wafer 100 in the via-etching is significantly reduced. This range of the reverse de-chuck voltage is likely to be less negative than the low reverse de-chuck voltages that are also used for de-chuck, which low reverse de-chuck voltages may be about −1300V, for example. The reverse de-chuck voltage may be applied, for example, about 2 seconds, although a longer or shorter time may also be used.

After the de-chuck process, lift pins 14 are raised to lift up wafer 100. Lift pins 14 are grounded and contact the backside of wafer 100. Accordingly, charges that are accumulated in the exposed conductive features may be discharged through the backside of wafer 100. Advantageously, due to the use of the high reverse de-chuck voltage, which has a magnitude of about 50 percent to about 75 percent of the low reverse de-chuck voltage, the JTAG failure is significantly reduced. Experiments performed on wafers have demonstrated that if a low reverse de-chuck voltage of −1300V (which was used in conventional via-etching processes) is used, after the formation of opening 22 (FIG. 3) and the subsequent photo resist ashing, the voltage potentials on the respective wafers range between about 6.5V and about −0.1V, with the difference being about 6.6V. As a comparison, when a high reverse de-chuck voltage of −975V (an embodiment of the present invention) is used, after the etching and ashing process of opening 22, the voltage potentials on the respective wafers range between about −1.3V and about −3.9V, with the difference being only about 2.6V. The significant reduction in the differences of voltage potentials on a same wafer indicates better charge neutralization in the embodiments of the present invention than in conventional methods, which results in lower JTAG failure rates.


Best,
Noah

> On Mar 4, 2015, at 10:49 AM, Bob Henderson <bob.henderson at etchedintimeinc.com> wrote:
> 
> Rick:
>  
> Holy lightning bolt you do seem to have a discharge problem. You didn’t say if the wafer has oxide on both sides but assuming it does I would suggest stripping the oxide on the chuck side to avoid the charging problem you seem to have. An electrostatic chuck works much better if you have a conductive material or in this case a semiconductor material than a dielectric. Assuming you also helium backside cooling with your E-chuck this should also allow you to etch the oxide that is patterned without the need to run multiple cycles. Depending on the RF power you might have to lower it a bit to avoid reticulation of the photo resist. I also don’t understand why you are using 8 microns of resist as 1-2 microns should suffice assuming the resist: oxide selectivity is around 3:1. If you care to share your process recipe I might be able to help out some more. Bob Henderson
>  
> From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Morrison, Richard H., Jr.
> Sent: Wednesday, March 04, 2015 5:08 AM
> To: labnetwork at mtl.mit.edu
> Subject: [labnetwork] Need help with RIE process
>  
> Hi everyone,
>  
> I have a strange problem that I need some help with. We have an  Ulvac NE-550 RIE system with an electrostatic chuck. The wafer is a double sided polish with 1um of SiO2. One side has an AZ4620 resist pattern 8um thick to etch the 1um of oxide. Because the process runs hot we break the etch into 9 different steps and move into the LL after every step. On the polished side that is down on the ESC check we have craters on the surface that look like a lightning strike or meteor strike, this is fairly deep several microns.
>  
> I have attached a photo of the damage. Have any of you seen anything like this? I need to fix the issue because the side that is down ends up being the frontside of the wafer and that is a killer defect. We think the oxide is charging and when the lift pins come up (at ground potential) we get a discharge.
>  
> Rick
>  
>  
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