[labnetwork] 200mm Bulk Silicon Etch Process Needed

Liam Boodhoo L.A.Boodhoo at southampton.ac.uk
Fri Sep 15 07:05:35 EDT 2023


Hi Randy,

My colleague Owain Clark passed this on to me. My name is Liam Boodhoo, I am the ECSP Commercial Processing Manager at the Southampton Nanofabrication Centre. This looks like something we can possibly help with. Can you confirm a few things for us to be sure?


  *   Do the wafers have active devices on the other side of the wafer?
  *   Can we use sacrificial protective layers on the other side?
  *   Are there any metals that are silicon carrier lifetime killers (like copper for example)?
  *   Is an edge exclusion acceptable for this process?

If a call is a quicker way to share information, we can set that up.

Many thanks,
Liam


Dr Liam A. Boodhoo
ECSP Commercial Processing Manager
Southampton Nanofabrication Centre
University of Southampton
Southampton
SO17 1BJ
UK

Phone: +44 (0) 23 8059 2650
Email: L.A.Boodhoo at Southampton.ac.uk<mailto:L.A.Boodhoo at Southampton.ac.uk>




From: labnetwork <labnetwork-bounces at mtl.mit.edu<mailto:labnetwork-bounces at mtl.mit.edu>> On Behalf Of Randall Parker
Sent: 14 September 2023 17:41
To: labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu>
Subject: [labnetwork] 200mm Bulk Silicon Etch Process Needed

CAUTION: This e-mail originated outside the University of Southampton.
We have a need to etch a thin layer of silicon off of 200mm wafers. The silicon layer is freshly ground and unpatterned. Etch needs to have sufficient oxide selectivity to stop within a buried oxide layer which is 0.2-1.0um thick. Entire silicon layer needs to be removed (ex. no edge exclusion due to clamping ring).

Requested etch is similar to removing a 10um device silicon layer off an SOI wafer and stopping in BOX layer...

Open to wet or dry etch methods. If wet,  single-sided processing is preferred to prevent etching back of wafer, but a tank etch is acceptable if a viable option exists.

Can anyone point me towards a service or lab facility that could perform this etch in low volumes (10-12 wafers/month)?

Thanks for your input.

Randy Parker
Sr. Process Engineer
American Semiconductor, Inc.
208-336-2773, ext 23

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